CLC-P1.1 Bosch Rexroth Indramat
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The Bosch Rexroth Indramat CLC-P1.1 is a motion controller from the CLC Motion Controllers series equipped with a 68EC020 CPU clocked at 25.0 MHz and a 68882 math coprocessor. It provides 512 Kbytes of battery-backed SRAM, features 4096 bytes of dual-port RAM, and supports two serial ports. The controller also includes 1 Mbyte of EPROM capacity with two EPROM sockets.
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Product Description:
The CLC-P1.1 is a motion controller produced by Bosch Rexroth Indramat within the CLC Motion Controllers series. It coordinates axis movement through a SERCOS fiber-optic ring, providing one input channel and one output channel for deterministic drive communication. By executing compiled application code, the unit supervises servo positioning, interpolation, and logical sequencing in industrial automation cells.
The controller is built around a 25.0 MHz Motorola 68EC020 CPU that handles instruction flow, while a dedicated 68882 math coprocessor accelerates floating-point calculations needed for trajectory generation. Program firmware resides in two EPROM sockets with an aggregate capacity of 1 Mbyte; this non-volatile memory stores the real-time kernel and user tasks. Rapid data exchange with drives is helped by a dual-port RAM of 4096 bytes, permitting asynchronous access from both the controller and peripheral masters. Two serial ports support diagnostics or HMI links, and the module exposes 512 16-bit registers for parameter passing, backed by type-specific areas that can hold 256 global integers and 256 global floats.
Runtime variables survive power loss because a battery-backed SRAM of 512 Kbyte retains machine states between cycles. Logic supply demands are modest: the 5 V rail draws 800 mA during peak processing, and the auxiliary 12 V rail requires only 20 mA for transceiver biasing, which simplifies power-supply sizing inside control cabinets. Register access is organized on a 16-bit data bus, matching the processor’s native width and enabling deterministic, word-aligned reads and writes. A register map of 512 locations allows firmware to segregate motion status, command queues, and safety interlocks without overlap, while SERCOS telegrams propagate axis feedback through the single input channel and broadcast setpoints through the paired output path.
Frequently Asked Questions about CLC-P1.1:
Q: What is the CPU clock speed of the CLC-P1.1 motion controller?
A: The CLC-P1.1 features a CPU running at 25.0 MHz.
Q: How much battery-backed SRAM is available on the CLC-P1.1 controller?
A: This model is equipped with 512 Kbyte of battery-backed SRAM for reliable data retention.
Q: How many EPROM sockets does the CLC-P1.1 have, and what is their combined capacity?
A: The CLC-P1.1 includes two EPROM sockets with a total capacity of 1 Mbyte.
Q: Which math coprocessor is used in the CLC-P1.1 controller?
A: A 68882 math coprocessor is integrated into the CLC-P1.1 for enhanced computation.
Q: How many SERCOS inputs and outputs are provided on the CLC-P1.1?
A: This motion controller offers one SERCOS input and one SERCOS output.