3CP360 B & R Automation
Wake Industrial LLC is not an authorized distributor of this product.
The B & R Automation 3CP360 is a controller from the System 2005 Controllers series featuring a Pentium 266 processor and 32 megabytes of DRAM. It includes three base unit slots, an APCI slot, and supports ATA or True IDE CompactFlash storage. The controller offers Ethernet connectivity via an RJ45 socket, supports 100 Base-T standard, and features a 9-pin DSUB RS232 connector with a maximum baud rate of 115.2 kBaud.
Internal Product Review
The 3CP360 is a System 2005 controller built around a Pentium 266 processor with a 0.02 µs instruction cycle time. An RJ45 socket with 100 Base-T Ethernet and a 9-pin DSUB RS232 interface support straightforward machine and service connectivity. With 32 MByte DRAM and 512 KByte L2 cache, the controller feels responsive in control tasks and remains a capable platform for legacy automation systems.
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Product Description:
The 3CP360 is a central processing unit module supplied by B&R Automation for the System 2005 Controllers series. Within an automation rack, it acts as the execution core that interprets ladder logic, structured text, or machine code and coordinates I/O, motion, and network tasks for discrete or process equipment. By integrating memory, a real-time clock, fieldbus connectivity, and local expansion interfaces in one housing, it provides deterministic control without the need for external PCs, making it suitable for compact machine applications and retrofit projects.
The module’s computing platform is a Pentium 266, giving 32-bit architecture and compatibility with x86 instruction sets used in B&R development tools. Its onboard memory includes 32 MByte of DRAM for dynamic data structures and code execution. Each Boolean or arithmetic instruction is completed in 0.02 µs, so high-frequency PID loops remain stable even with large program sizes. For factory networking, the controller exposes a single RJ45 port that follows the 100 Base-T standard, permitting Ethernet/IP or Modbus TCP traffic at full-duplex 100 Mbit/s. Local specialty cards such as high-speed counters are added through 1 APCI slot, while three base-unit positions plus four additional positions accept standard System 2005 digital or analog terminals.
Serial diagnostics and legacy device links are handled by the embedded D-sub port, which sustains transfers up to 115.2 kBaud, so parameter files or G-code streams load quickly. A secondary cache of 512 KByte reduces latency between the CPU and SDRAM during repetitive matrix operations. For recipe data that must survive power cycling, the controller provides 256 KByte of remanent variable space in nonvolatile SRAM. Time stamping of alarms relies on an RTC with 1 s resolution, which is adequate for batch and shift logging in packaging, textiles, or woodworking cells.
